MiSTer FPGA Forum

I can't seem to locate this answer. What's the reason that MiSTer can't have a 256MB RAM stick? Is it a hardware or software limit? A physical addressing issue? Something else?

I'm aware that in the future using two 128MB sticks may be needed, but I'm curious the technical reason we're stuck at 128MB per stick.

Thanks for any insight.

The largest single-data-rate SDRAM chip that's readily available is 64 megabytes - the 128 meg module has a pair of them, and is already pushing the limits in terms of signal integrity. Also, because of a lack of IO pins, instead of each chip having a select signal, a single select is inverted for one of the two chips. To add another pair of chips for 256 meg you'd need to find a way to give each chip its own select signal, and then hope that the extra load of two more chips wouldn't push the already-marginal signal integrity over the edge.

The limitation the newest cores will bump into isn't actually size, though, it's access time - so having more memory on the far side of the same bottleneck wouldn't actually help.

That's exactly what I was looking for, thank you.

teknomedic wrote: ↑Mon Oct 11, 2021 7:13 am I'm aware that in the future using two 128MB sticks may be needed, but I'm curious the technical reason we're stuck at 128MB per stick.

Thanks for any insight.

AFAIK the reason for using 2 memory sticks is more to do with bandwidth than capacity for the systems MiSTer is looking to implement.

The GPIO pin header is a limiting factor for bandwidth.