MiSTer FPGA Forum

Posted: **Sun Nov 07, 2021 3:04 am**

At least on Windows, I'm getting white-space diffs due to line ending changes when I build. Am I missing something obvious here? Is there a way to turn this off.

Wait, I'm not sure now. Maybe it's git Windows/Linux confusion that's screwup on my line endings. Hmmph

Posted: **Sun Nov 07, 2021 5:03 pm**

It’s probably Windows/Linux confusion unless your editor is forcing a particular indentation method.
I find that GitHub Desktop deals with that line ending stuff OK.

Posted: **Mon Nov 22, 2021 1:21 am**

Oops, VHDL is not case sensitive, but verilog is. (Still working through little quirks like this.)

MiSTer FPGA Forum

Quartus Prime is monkeying with line endings?

Quartus Prime is monkeying with line endings?

Re: Quartus Prime is monkeying with line endings?

Re: Quartus Prime is monkeying with line endings?