Renesas plans to ship small real low cost FPGA

[Chris23235]

Renesas plans to ship a sub 50 cents FPGA (if you order a high volume).

https://www.cnx-software.com/2021/11/22 ... ent-tools/

They state the power consumption as sub 20uA and it is planned to have 5000 logical gates.

I wonder if this would be enough to fit a Gameboy core into such FPGA? With this price and power consumption It would make a great fit for an FPGA handheld.

[softtest9]

I always thought that it would be cool to have a game console with a CPU paired with 1-3 FPGA chips for things like graphics and sound. The console could then evolve to fit the needs of its games, or just be reprogrammed by individual games.

Developers who prefer working with "real" sprite hardware could have that and developers who prefer to work with a frame buffer could go with that instead, for example. And they would all be targeting the same basic platform.

I wonder if this would be possible with these FPGAs.

[N.Master]

Hi,
Those chips are interesting for small apllications but 5000 logical gates is a bit weak for emulalting a processor or coprocessor
For comparison the cyclone V has 110 000 logical gates + dual arm cortex A9 processor

So it's nice to have small FPGAs for glue logic or small ASICs, or to handle small time-critical tasks, but it's too small for emulating an handheld console (Except maybe a game&watch)

However, the great news is "the Renesas development tools will be completely free, and without the hassle of having to install license keys"
that feature + the low price makes it possible to create a very cheap developpement board for FPGA beginners

And maybe in the future Renesas will make a bigger FPGA

[ExCyber]

The size of these devices seems hard to pin down without an proper overview of the architecture. In one place, the article says that "the first devices ship with 1K and 2K Look Up Tables". In another place, it says that the SLG47910V has an array "[e]quivalent to 900 4-bit LUTs". I'm not sure which of those is being equated to 5000 gates, but modern FPGAs don't usually specify a gate count because on most architectures that's more of a marketing exercise than an objective measure. The 110,000 number for DE10-Nano's chip is "logic elements", which in turn seems to be fudged from the count of the actual layout element, the ALM (Adaptive Logic Module, each of which contains an 8-input fracturable LUT, two full adders, and four registers). The ratio is roughly 2.6 logic elements per ALM. I guess it's just hard to directly compare such drastically different architectures.

Also, has the memory technology been confirmed anywhere? I doubt that they'd market these as "FPGA" devices unless they were reprogrammable, but some FPGA families are based on EEPROM and have a fairly limited number of write cycles (e.g. 1000). That would be great for a dedicated clone product, but not so much for a framework like MiST/MiSTer.

If they're expected to be in mass production in Q2 2022, I suppose the datasheet will be out before too long.

[dshadoff]

The product line is planned up to 5000 gates, but they haven’t announced all of the devices yet.
To me, there are two key takeaways:
1) These will be great for discrete logic consolidation, simple state machines, and overall cost-down on electronics which are not so complex (but still a 1980’s ASIC complexity)
2) General trend toward lower cost devices will continue across more complex devices over time.

Hobbyists should be able to make some seriously interesting things without breaking the bank.

[aberu]

I fired up the development tools, you can already use them. Nice UI overall. It's kind of like the interface from a PLC software suite, which makes sense since it's able to do that as well.

[dshadoff]

Yes, but the datasheet for the first part is still not available… so the only information we have right now is a pinout in that tool.