MiSTer FPGA Forum

Hi all,

Is it feasible to implement 32-bit cores in MiSTer?

I was looking for a way to get NextStep on to MiSTER and came across this project:

http://temlib.org/

It's basically an implementation of sparc32 in fpga.

From the website:

"There is also an unfinished version (complete but with bugs) for an Altera CycloneV GX (Terasic “Cyclone V GX Starter Kit”)

+——————————————————————————+
; Fitter Summary ;
+——————————————————————————+
; Device ; 5CGXFC5C6F27C7 ;
; Logic utilization (in ALMs) ; 9,490 / 29,080 ( 33 % ) ;
; Total registers ; 11070 ;
; Total pins ; 324 / 364 ( 89 % ) ;
; Total block memory bits ; 560,896 / 4,567,040 ( 12 % ) ;
; Total RAM Blocks ; 83 / 446 ( 19 % ) ;
; Total DSP Blocks ; 5 / 150 ( 3 % ) ;
; Total PLLs ; 1 / 12 ( 8 % ) ;
; Total DLLs ; 1 / 4 ( 25 % ) ;
+———————————+——————————————–+"

http://temlib.org/site/?p=567

He already has a MISTer implementation on his ftp site (http://temlib.org/pub/mister/SS/) which boots but so far I have been unable to do anything as the zips for NextStep, Solaris and another OS are password protected.

Ok, excellent. I missed that.

I'm going to give it a try.

Do you know if those are OS images or virtual disk images?

If it's the OS's - an ISO is available here:

https://winworldpc.com/product/nextstep/3x

I have no idea about the OS images and I did not spend much time on it.

Ok, I'll attempt to contact the author directly.

The Archimedes was using a 32 bits RISC CPU and got a core on the MiSTer.

The passwords are the OS names. Uppercase and lowercase characters.

I'm trying to finish the SMP version a.k.a SparcStation 10/20, with coherent MESI write-back caches.

(Yes I'm the author)

This is exciting stuff @Grabulosaure!

I'll try this core shortly and give feedback.

@Grabulosaure, I downloaded nx.tar.xz.zip which I assume in the NextStep image. I'm still trying to figure out the password though. Tried various combination "NextStep" - are you able to provide these in the forum, or should I e-mail you directly at info@temlib.org?

@antonie
Wikipedia...

It took me a while to figure it out. You have to type the official name exactly as it is.

Ok, cool

During my short lunch break I started to boot Solaris. I got a warning regarding last shutdown more recent than current time (Y2K?).
Last line displayed Hostname: solo.
I did not have time to figure out what to do next. May be ^D?
Now I also figured out that the sos archive is Sun OS.

Sun OS boots fine, I still must try Solaris. NeXTSTEP seems a bit unstable.

BTW I had to boot from the OpenBios command line. I figured out that, at the prompt, you must first select the .raw image before the "O> boot" command.

@Grabulosaure this is really good work...helping to push the MiSTer "state-of-the-art" even further forward. The community is getting exposed to machines that were (for me anyway) quite out of reach.

@Grabulosaure your SS core is fantastic! Thank you. Are you planning to release it in the source code or are there any obstacles to this? I am a fan of the UNIX RISK systems. And I think that MIster really misses them.

This is a great core. The Solaris and SunOS both work great, particularly Solaris, which seems tp run perfectly. With Solaris, just wait (there is a lot of waiting with this core) until you get a graphical login screen and then log in as root.
NextStep seemed problematic, The first couple of times that I tried loading it, it got all the way to the desktop, and then stopped with an error. Just now, it seems to have loaded correctly for the first time.
Anyway, thanks for the great work on this core. It's lots of fun.

D.

The Amiga core (Minimig) is also 32-bit, FWIW.

@danielb

There are old sources available for the Xilinx SP605 board. But many things have changed since then.
I would like to clean-up sources and finish SMP mode before releasing them.

For those really interested, there is also a debugger ("debug". Ha!) which can be run from MiSTer console (SSH or direct access).
The debugger will show boot messages and make startup a bit less boring.
It can also stop the CPU, read registers, dump memory, place breakpoints... a bit like a JTAG debugger.

Booting is very slow because cache is disabled at some times during boot, due to compatibility and memory coherency issues.
And OSes like Solaris never tried to reduce boot time for computers which were usually always-on.

@limi
But MiniMig doesn't have (yet) a pipelined IEEE 754 single/double precision FPU !

Grabulosaure wrote: ↑Fri Jul 03, 2020 9:08 pm @limi
But MiniMig doesn't have (yet) a pipelined IEEE 754 single/double precision FPU !

And all 680x0 core dosen't have MMU. that does not run unix on them!

@Grabulosaure do you plan to make ethernet works? I see there are two vartants 1. bring the virtual adapter to the Linux HPS (ARM) side or 2. connect to free GPIOs like ENC28j60

xolod79 wrote: ↑Fri Jul 03, 2020 10:32 pm
And all 680x0 core dosen't have MMU. that does not run unix on them!

MMU present since 68030 (not EC or LC).

IIRC 68K first external MMU, MC68451, was almost as wacky as x86 protected mode.
Then Motorola went saner, removing features, to eventually leave in MC68040 only things used by UNIXes and MacOS.

@xolod79
There is an Ethernet MAC (AMD LANCE based) that used to work with the PHY on the Xilinx board.
A direct connection to a MII/RMII PHY (such as LAN8720 modules) should be easy.
For MiSTer, IDK. Maybe transferring Ethernet frames to the serial port to be handled by some bridge software.
Or find how to do PPP on Solaris, SunOS, Linux, NextStep...

Grabulosaure wrote: ↑Fri Jul 03, 2020 9:08 pm @limi
But MiniMig doesn't have (yet) a pipelined IEEE 754 single/double precision FPU !

Indeed! No FPU or MMU in the 68020 series. And as you pointed out, the 040 architecture was way more sane in this area than the 030. But, still 32-bit

limi wrote: ↑Sat Jul 04, 2020 2:17 am

Grabulosaure wrote: ↑Fri Jul 03, 2020 9:08 pm @limi
But MiniMig doesn't have (yet) a pipelined IEEE 754 single/double precision FPU !

Indeed! No FPU or MMU in the 68020 series. And as you pointed out, the 040 architecture was way more sane in this area than the 030. But, still 32-bit

There were external FPU and MMU for the 68020.

Anything wrote: ↑Tue Jul 07, 2020 1:58 pm

limi wrote: ↑Sat Jul 04, 2020 2:17 am

Grabulosaure wrote: ↑Fri Jul 03, 2020 9:08 pm @limi
But MiniMig doesn't have (yet) a pipelined IEEE 754 single/double precision FPU !

Indeed! No FPU or MMU in the 68020 series. And as you pointed out, the 040 architecture was way more sane in this area than the 030. But, still 32-bit

There were external FPU and MMU for the 68020.

I had a 68882 with my 68030.

Anything wrote: ↑Tue Jul 07, 2020 1:58 pm There were external FPU and MMU for the 68020.

Yup! I should have said “on the chip”, which is what I meant, since it didn’t have e.g. MMU built in like the 030 and 040. (EC versions excepted)

(But we’re a little off the original topic now)

I have an archive of most versions of SunOS, Solaris, NeXTStep, and OpenStep if you need them for testing.

Sorgelig wrote: ↑Fri Jul 03, 2020 10:52 pm

xolod79 wrote: ↑Fri Jul 03, 2020 10:32 pm
And all 680x0 core dosen't have MMU. that does not run unix on them!

MMU present since 68030 (not EC or LC).

I wanted to say that. I am not aware of more than one open source MMU implementation for 680x0.

There is also an interesting proposal to implement a virtual ethernet adapter using a TAP device. what will require adding to the Mister framework a service for transferring ethernet packets between fpga and HPS (probably through shared memory?). just like it was done with sound cards. This solution will allow it to be used for other cores Minimig, Ao486 and others. I know that this is obvious to many, do not scold me.

I do have a spare station 10 which I think I a had dd image of running Nextstep. Dunno if that would help anyone. The Risc NS OS install images about are all DD images, no passwords on those. The SS10 is not a NS machine at the mo as it has an unsupported processor card inside right now.

I giggled like a child, when I brought up SunView....brought back old memories.

How hard would it be, to get networking going ? Is this a problem that'd impact most projects ?

@bigvalen

Some cores support networking though serial port (PPP...) : Amiga, AO486. The SparcStation core also has an internal serial port accessible from Linux side, it can be used for the console and hardware debugger ("debug" ARM executable), it could be used for networking.

Networking worked on the old Xilinx dev board with had an MII PHY. A RMII PHY requires 7-8 signal pins.