MiSTer FPGA Forum

I’m working on a Workbench 1.3 setup that is essentially equivalent to an Amiga 500 with an attached A590 hard drive.

On Workbench 1.3, you’re supposed to be able to retrieve the current time/date from the RTC using the setclock command. I’m not using the RTC module, just network NTP time, by the way.

This works great on a Workbench 3.x setup with the core configured close to an Amiga 1200 setup, as well as a Workbench 2.x setup with the core configured close to an A500Plus/A600.

However, when running setclock on 1.3 (it’s the latest version from Aminet, I know that earlier versions had Y2K bugs), I get the following on MiSTer:

Code: Select all

1.SYS:> setclock
Battery Backed up Clock not found
1.SYS:>

Is anyone else successfully using the “battery backed up clock” (NTP in this case) under Workbench 1.3?

I think the RTC chip implemented on the core is newer than 1.x-compatible SetClock versions expect. I tried the SKS A3000 1.3 SetClock and it didn't work either.

Thanks for verifying. Filed a bug: https://github.com/MiSTer-devel/Minimig ... issues/160

I’m working on a Workbench 1.3 setup that is essentially equivalent to an Amiga 500 with an attached A590 hard drive.

I was trying to duplicate your bug, but I can't figure out how to boot a hard drive from Kickstart 1.3 on Minimig. The only hard drive type offered is A600-style IDE, and my 1.3 ROMs won't boot from there. Are you booting from floppy, or doing something else unusual?

Malor wrote: ↑Sun Feb 12, 2023 4:35 am

I was trying to duplicate your bug, but I can't figure out how to boot a hard drive from Kickstart 1.3 on Minimig. The only hard drive type offered is A600-style IDE, and my 1.3 ROMs won't boot from there. Are you booting from floppy, or doing something else unusual?

You need to patch the Kickstart to get that support, the A590 shipped with a way to modify the system to boot from HD (was included from 2.0 onwards).

In any case, you can reproduce the bug from a floppy disk image of 1.3.4 too.

Yeah, I just didn't have any floppy images convenient. I'll copy some over from WinUAE.

edit: I get the same error. As an extra test, I tried adding 512K of slow RAM, in case it was working like the actual A500 did, with the RTC on the trapdoor expansion. Made no difference.

The RTC is not really implemented. The HPS side supplies the necessary data, but writing to the RTC chip is not supported. So, if the setclock program does some probing, it will conclude that there is no RTC clock.

Interesting that it works on the exact same hardware configuration using Kickstart and Workbench 2.0, though.

Interestingly, if you boot Workbench 1.3 on a 2.0 Kickstart, setclock works as expected. It therefore seems to boil down to how setclock interacts with the Kickstart. Implementing a complete OKI clock IC seems to be a waste of time. It's probably easier to write a replacement for setclock, which just reads the RTC clock and asks no further questions.

I had a quick look at the disassembly of setclock and it indeed writes to the clock chip. But that might be of no consequence. At some point it checks if the seconds register has advanced after a syscall. That piece of code might be a candidate for the problem.

I patched the detection routine. The attached version works on Kickstart 1.3, but will assume that there is a real time clock. Which is always correct for Minimig on MiSTer, but might crash systems without RTC (since then it will access the custom chips).

Thank you! Works great, and I can definitely use this and put some checks on it to make sure it doesn’t run on non-MiSTer setups.

R4M wrote: ↑Tue Feb 14, 2023 12:00 am

Interestingly, if you boot Workbench 1.3 on a 2.0 Kickstart, setclock works as expected.

Isn’t this because it’s handled automatically in 2.0 onwards? When I boot 2.0/3.x without a startup-sequence and issue the date command, it has the correct date and time.

I found the problem: the MiSTer binary only updates the rtc time once a minute... and the 1.3 SetClock checks for a change in the seconds register after waiting for 1.5 seconds... a solution would be to incement the rtc counter on the hps side inbetween. I'll have a look into it.

Sorgelig fixed it. Should work with stock SetClock in next release.

Fantastic, thanks!

The fix is in the official core now — thanks for identifying the solution, R4M!

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