MiSTer FPGA Forum

@nico24,

Thanks for the new episode!

https://m.youtube.com/watch?v=Q6-rZlDPxug

Thank you @Alkadian. The animations took a LONG time....all that for about 5 minutes video..

nico24 wrote: ↑Mon May 29, 2023 1:36 pm

Thank you @Alkadian. The animations took a LONG time....all that for about 5 minutes video..

@nico24,

I am following your new series with deep interest! I can clearly see all the efforts that you put in your videos as I do appreciate that it takes a lot of time to achieve that level of detaIls and quality that you always delivery in each of your episodes.

I took note of what you said about using the same master clock for all the ALWAYS blocks and then using clock enable signals to trigger the counting to avoid some clock skew.

Thanks a ton for sharing your knowledge!

Thanks! Yes in the Enigma 2 core, that is in 'stasis' at the moment (works but can't get sound), I got very bad results doing this daisy-chain and I can go through that at some point, showing how the two versions work. The main annoyance is that if you get borderline timing with FPGAs then the output changes based on how you monitor the wires in SignalTap, and that can be very frustrating!