MiSTer FPGA Forum

I am not a coder but I attempted to find any information on if Cyberball would be getting a core. I am just now getting into the MISTer so if this is in the wrong place or wrong context please excuse me. And I salute those that have the skills to make this project the success it has become. I hope that eventually most if not all of the arcade machines are able to be preserved this way. I won't disparage any of the other companies making so-so arcade cabs but if the product isn't true to the original it isn't the original.

I'm not aware of anyone working on it right now. As a lot of arcade hardware is custom they have to be handled on a case-by-case basis and unfortunately Cyberball and Cyberball 2072 don't appear to be directly derived from any other boards but do have some common components (68000, 6502, YM2151 etc).

At least you can play the many home console/computer ports on MiSTer for now?

PCB : A044283 CYBERBALL
Main CPU : 2 x 68000P8 @ 7.15909 & M6502 @ 1.789772
Sound chip (Kit) : Stand-Alone Audio II (6502 @ 1.790 MHz, driving YM-2151 + OKI 6295)
Sound chip (Dedicated) : 68000 driving YM-2151 @ 3.579545 + DAC
ROM : 136064
Oscillators : 14.31818
Other Chips : 8845, 137419-104 [40pin DIP, 13N/13M]
Motorola : SOS, 137550-001 [40pin DIP,24B/25B/14K/14M/16M/12N/12M]
Motorola : VMA, 137552-001 [40pin DIP, 8A/9A]
Video resoution : 672x240

So a dual 68k system

http://system16.com/hardware.php?id=771

Please do not misunderstand, I am humbled by the amount of games and work that is represented by this (not sure what other to call it) project. I just really love the idea that this might very well be the way that future generations are able to experience the wonder that I had as a youth. I mean I seriously doubt that ANYONE could ever curate and maintain these 'one off' computers with any real level of competence, especially given the sheer number involved. I won't even mention the small nuclear power plant that it would require. I was just floating the idea that this would be another one to Possibly add to the list in the future. I am doing good to catalog my games collection so that I can finally enjoy the real thing again.

FPGA64 - As I am EXTREMELY new to the scene- I love the url and pictures but I am not sure what other than raw data that your post is about.

Generally the more chips and the faster they are the harder it will be to fit it into a DE10.

FPGA64 wrote: ↑Sun Aug 06, 2023 2:43 pm

Video resoution : 672x240

Nothing about those specs indicate it would be a particularly difficult game to implement except for this. Cyberball was a double cabinet with two displays, so an implementation would have to account for this and maybe even used the analog and digital split that the 2 player GB/GBA cores use. There's a single-screen Cyberball 2072 cabinet so that would be less of a problem.

Mr. Encyclopedia wrote: ↑Thu Aug 10, 2023 1:17 am

FPGA64 wrote: ↑Sun Aug 06, 2023 2:43 pm

Video resoution : 672x240

There's a single-screen Cyberball 2072 cabinet so that would be less of a problem.

This Single monitor Cabinet is what I was envisioning to be presented as I have doubts that a multi-monitor multi-mister setup would be feasible for any but the most dedicated in the community.
Again, I'm interested in maintaining for the public what I loved as a child/young adult, as I'm sure others here are. I sincerely doubt there will be a working Pac-Man cab in 30 years, let alone a Cyberball or Gorf.

And to the folks that are working on these projects- I have a question. Is it possible for Anyone to get involved in the coding? I learned Basic back in the late 80's and I still do a bit of Batch file work for my job.

FPGA and conventional programming are different beasts. You can do both but FPGA seems to need you to be able to read HW schematics and be aware that all the FPGA code is executed at the same time unlike standard procedural programming.

Having a degree in electronics I can read a schematic but simultaneous execution baffles me. I haven't seen many Real Arcade boards but those that I have I seem to remember a clock crystal on them so timing would be sequential not simultaneous, unless I am missing something and no I don't have a schematic to ponder either so I could be mistaken. But my curiosity drives me to ask questions.

In FPGA programming there is a clock. On the Rising or falling edge of the clock everything gets evaluated at the same time but the results wont be available until the next clock. So you have to get used to knowing your result wont be available, but when you read the FPGA code its strange knowing its acting on the last cycles values. That bit always makes my mind rebel.