MiSTer FPGA Forum

I've been trying to find a way to add padding to the left and right sides of a core's image before it gets scaled (this allows for soft rather than razor-sharp edges). I've been able to do this for some individual cores by fiddling with the DE/HBlank signals, but that doesn't always work and I'd like to have a more general solution anyway, hence ASCAL.

I've figured out how to increase the input line width:

IF i_iauto='1' THEN
    -- Auto-size
    i_hmin<=0;
    i_hmax<=i_himax+4; <<<<<
    i_vmin<=0;
    IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN
        i_vmax<=i_vimax;
    END IF;
ELSE

However, there's no obvious way to center the core output within the increased width, so I can only pad the right side. Any ideas? I'd want to add two pixels of padding on each side regardless of the core's output width.