Hello,
maybe this is a bit off topic for MiSTer, but maybe some experts on the C64 FPGA implementation may help me by finding an answer which is/was also of interest by the FPGA implementation of the great C64 core.
I am currently working on an implementation of the C64 using the neo6502 hardware and I noticed that on RESET, the C64 the Kernal routine at $FCE2 is called. First thing it does is it disables all interrupts (SEI), so no interrupts will be handled. Later in the reset routine, a decision is made about PAL or NTSC and based on this the CIAs are programmed according to the required timing. For this decision a flag is used at $02A6. After this flag has been read out and the CIAs have been programmed, finally the VICII is initialized for the first time setting register $D01A to 0 (value is a lookup table in rom). After that the VIC seems to be programmed to create an IRQ at the 311s line using $d012 and $d011. However, no IRQ should ever occur here because no CLI has been executed after the SEI and in $D01A raster interrupts are still disabled ($D01A is still 0) and I did not find any code in the Kernal where it is enabled again. Furthermore, due to the fact that the VICII is initialized after reading out $02A6, the PAL / NTSC detection should not work at all. Does anybody know why this works or is it simply a don't care bug? Thank you in advance.