MiSTer FPGA Forum

Does anyone know the exact latency requirements for SRAM? I can't find it anywhere, only that it's less latency than the DDR3.

The Alliance SRAM used on the 128MiB board has 3 cycle CAS at 143MHz, about 21ns; that doesn't account for row precharge, row-to-column, etc.. It's also $13 per chip, and you need 2.

New HyperRAM at 250MHz has 28ns initial latency (7 cycle at 250MHz) but occasionally bounces an additional 4-cycle latency period (16ns), giving a maximum 44ns latency. This sounds pretty good, since you can just adapt to the occasional extra latency period by pausing the core (that's approximately what happens anyway as far as I can find online); except the 512Mbit HyperRAM modules are actually two 256Mbit modules glued together, and they have a mandatory extra latency period, so every access is 44ns latency.

Cost for 128MiB is $7.25. The data bus speed is actually about twice as high as the SDRAM module, not that that matters.

Engineer experiences suggest HyperRAM is a bit more sensitive than SDRAM, i.e. an expansion card might be harder to make function in the high speed modes; but I'm more interested in designing a single purpose-built PCB for MiSTer than continuing with cobbled-together parts. What exactly has to go on it depends on what kinds of timing constraints I need to hit.

HyperRAM, PSRAM (or whatever pseudo-SRAM memories) have hidden uncontrolled refresh cycles, so it's impossible to predict when it happens while simple SDRAM used in MiSTer allows full control of refresh making possible to squeeze originally impossible timings by hiding refreshes and sometimes go a little off-spec.
Thus, these modern pseudo-SRAM are not suitable for systems where precise exact timings are required.
Another downside of these chips are semi-serial bus requiring much higher clock to achieve the same random access time as legacy SDRAM. Current SDRAM is already hitting the limit of current hardware construction (de10-nano, connector) not chip itself, so rising clock further is basically impossible. Cyclone V also has about the same clock limits ~150MHz.

johninbaltimore wrote: ↑Sun Mar 10, 2024 9:52 pm

Does anyone know the exact latency requirements for SRAM? I can't find it anywhere, only that it's less latency than the DDR3.

The Alliance SRAM used on the 128MiB board has 3 cycle CAS at 143MHz, about 21ns; that doesn't account for row precharge, row-to-column, etc.. It's also $13 per chip, and you need 2.

New HyperRAM at 250MHz has 28ns initial latency (7 cycle at 250MHz) but occasionally bounces an additional 4-cycle latency period (16ns), giving a maximum 44ns latency. This sounds pretty good, since you can just adapt to the occasional extra latency period by pausing the core (that's approximately what happens anyway as far as I can find online); except the 512Mbit HyperRAM modules are actually two 256Mbit modules glued together, and they have a mandatory extra latency period, so every access is 44ns latency.

Careful there. You're using the term SRAM, which means "Static RAM", which is normally 1-cycle turnaround up to its rated response time (generally 10ns-70ns). BUT, there is no SRAM on MiSTer. You are probably talking about SDRAM, which is an entirely different thing, as Sorgelig already pointed out.

In order to understand SDRAM's latency, you should look at the product datasheet, where they will talk about how to access, and what types of latencies occur in various conditions... this is why a SDRAM controller is a non-trivial thing.

As for HyperRAM, don't assume that you would be able to drive it at anywhere near 250MHz. Anything over 100MHz will be challenging for a variety of reasons.