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ROM loading details

Posted: Tue Sep 10, 2024 2:08 am
by chiron40k

Hi,
I've grown very interested in the Mister project & interested in learn more in particular about the NES core. I'm trying to follow the process in how ROMs are loaded, from the user interface in Linux down to it being accessed from the CPU/PPU.

This is my understand so far... It looks like roms can be stored any place by a user of the Mister Project and load this via a UI. I don't have a Mister myself =/ not yet. The ROM is loaded from

=========================================

sys_top.v -> nes.sv -> hps_io -> gameLoader

in gameloader there are 4 file types:

wire type_bios = filetype[0];
wire type_nes = filetype[1];
wire type_fds = filetype[2];
wire type_nsf = filetype[3];

I'm not sure what bios means? But I believe nes is the ROM header, fds relates to the nes disk system, & nsf to a header related to sound

=========================================
gameLoader -> nes.v -> cart_top -> (to many module instances, once for each mapper)

in generic.sv, looking at mapper28 as an example
I'm trying to understand what the following signals are and how the relate to mapping the ROM/RAM seen by the NES

reg [6:0] a53prg; // output PRG ROM (A14-A20 on ROM)
reg [1:0] a53chr; // output CHR RAM (A13-A14 on RAM)

reg [3:0] inner; // "inner" bank at 01h
reg [5:0] mode; // mode register at 80h
reg [5:0] outer; // "outer" bank at 81h
reg [2:0] selreg; // selector register
reg [3:0] security; // selector register

Following this I believe the ROM is ultimately loaded into SDRAM. I think the mapper is designed such that
when the NES needs to access either ROM/RAM it is routed to via a mapper to locations in SDRAM that

don't change, regardless of the mapper used.


Re: ROM loading details

Posted: Wed Sep 11, 2024 12:22 am
by rhester72

Don't forget that before you even reach the FPGA, the actual loading process begins on the Linux side:

https://github.com/MiSTer-devel/Main_MiSTer


Re: ROM loading details

Posted: Wed Sep 11, 2024 2:06 am
by chiron40k
rhester72 wrote: Wed Sep 11, 2024 12:22 am

Don't forget that before you even reach the FPGA, the actual loading process begins on the Linux side:

https://github.com/MiSTer-devel/Main_MiSTer

Hi rhester72,
good point looking forward to booting into Linux once my board arrives =]