I had taken the approach of plumbing in the 'almost avalon slave' interface into the cpu_wrapper.v then basically plugging it in into the cpu selection mux to replace the fx68k. My initial approach had worked 'mostly' ok. I cleaned/tidied some stuff up and then ... nothing worked ... despite my signals appearing to be ok in signal tap.
I was thinking that the aga/ocs switch was independent of this cpu mux. So was confused by this not affecting chip ram speed via the minimig.
Seems like instead of putting it in the mux I should put it in in place of the tg68k for now and take advantage of all that plumbing. Though I will 'steal' fast ram accesses upstream on the arm side.
re: dtack vs sram vs sdram
In the m68k bridge I saw this:// synchronous control signals
Code: Select all
wire enable = ~l_as & ~l_dtack & ~cck;
assign rd = enable & lr_w;
assign hwr = enable & ~lr_w & ~l_uds;
assign lwr = enable & ~lr_w & ~l_lds;
Then in gary it plumbs it to ram_rd
Code: Select all
//read write control signals
assign ram_rd = dbr ? ~dbwe : cpu_rd;
assign ram_hwr = dbr ? dbwe : cpu_hwr;
assign ram_lwr = dbr ? dbwe : cpu_lwr;
